1. Field of the Invention
The present invention relates to the packaging of electronic components such as integrated circuits or other electronic devices. In particular, this invention relates to an improved semiconductor device package wherein at least one semiconductor die is encapsulated on a substrate and another volume of encapsulant material is added to the opposing side of the substrate in a configuration to assist in control of the stresses in the package.
2. State of the Art
Conventionally, semiconductor dice have been packaged in plastic or, less commonly, in ceramic packages. Packages may support, protect, and dissipate heat from semiconductor dice. Packages may also provide external connective elements for providing power and signal distribution to and from semiconductor dice, as well as for facilitating electrical testing, such as burn-in testing and circuit evaluation, of semiconductor dice prior to or after assembly thereof with higher-level components, such as carrier substrates or circuit boards.
FIG. 1A schematically illustrates a section of a conventional board-on-chip (BOC) semiconductor device assembly 100A with electrical contacts which conventionally comprise a ball grid array (BGA) of discrete conductive elements 12 such as solder balls. FIG. 1A shows substrate 4, typically a printed circuit board, mounted to semiconductor die 2. Semiconductor die 2 is placed in electrical communication with substrate 4 by bond wires 6 extending between bond pads 3 of semiconductor die 2 and terminal pads 5 through slot 7 in substrate 4 using conventional wire bonding techniques. Both semiconductor die 2 and bond wires 6 are encapsulated in a transfer molded, filled polymer volume of encapsulant material shown by die encapsulation region 8 and wire bond cap 10. FIG. 1B illustrates a side view and FIG. 1C illustrates a plan view of the semiconductor device assembly 100A of FIG. 1A.
FIG. 2A schematically illustrates a conventional chip-on-board (COB) assembly 200A fabricated using conventional wire bonding techniques. FIG. 2B shows a flip-chip configured semiconductor device assembly 200B that utilizes solder bumps 14 instead of wire bonds to electrically connect semiconductor die 2 to substrate 4.
A semiconductor die, the encapsulation material, the adhesives or other bonding agents used to connect the semiconductor die to the substrate, the substrate, and the electrical connection mechanisms between the semiconductor die and the substrate of a semiconductor device assembly are usually each made from a different material or combination of materials. These different materials usually have different thermomechanical properties due to differing coefficients of thermal expansion (CTE), which differences result in stresses developing during manufacture or use of the semiconductor device assembly, the latter due to thermal cycling. Several problems can result during manufacture and use of semiconductor device assemblies due to the development of these thermomechanical-related stresses. For instance, bowing of the semiconductor device assembly can occur due to internal bending stresses, causing cracking in the encapsulant materials and subjecting components to environmental degradation, debonding of the semiconductor die from the substrate, solder joint failure, or cracking in the substrate itself. Even if minimal bowing is manifested initially, residual tensile stresses can still be present, eventually resulting in the same problems after a period of time due to thermal cycling-induced fatigue experienced during normal operation.
Residual tensile stresses develop during manufacture from the aforementioned mismatch of material CTEs, as well as from shrinkage of the encapsulation material during curing and hardening thereof. FIG. 3 shows an exaggerated view of bowing in a wire bonded BOC assembly 100A as previously depicted in FIG. 1A due to the thermomechanical stresses. The bowing occurs in significant part due to the imbalance of the volume of encapsulant material between the two opposing sides of substrate 4. As shown in FIG. 3, there is significantly more encapsulant material volume present in die encapsulation region 8 than in wire bond cap 10. Further, die encapsulation region 8 extends completely across substrate 4, while wire bond cap 10 runs primarily longitudinally over substrate 4, extending laterally only a sufficient distance to cover bond wires 6 and slot 7. The resulting predominant tensile stress developed near substrate 4 and on one side thereof due to shrinkage of the substantially different volumes and extents of the encapsulant material applied to the opposing sides of substrate 4 can cause significant problems with respect to package integrity. One particularly notable problem is cracking in wire bond cap 10, which exposes the wires to environmental degradation and may itself cause breakage of the thin, delicate bond wires 6.
The prior art has attempted to address the issues of undesirable stresses in semiconductor packaging. For example, U.S. Pat. No. 5,627,407 to Suhir et al. purportedly solves the problem of unwanted thermomechanical stresses by using a thin “surrogate layer” on the entire substrate side opposite the encapsulated semiconductor die. However, this method utilizes significantly more material in the surrogate layer than may be needed and involves the use of a different material than the encapsulant. Also, by covering an entire side of the substrate with the surrogate layer, it is difficult, if not impossible, to place discrete conductive elements, such as a BGA, on the substrate side bearing the surrogate layer. Further, adding this surrogate layer may be required to be performed as an additional process step. Little guidance is provided as to how the encapsulant and the surrogate layer might be applied concurrently, as is indicated by Suhir as being a desirable approach. In addition, placement of a surrogate layer proximate each substrate and prior to encapsulation will itself require additional cost and alignment considerations.
U.S. Pat. No. 6,294,831 to Shishido et al. attempts to reduce bowing in a flip-chip type semiconductor device assembly by bonding a structure over the back side of a flip-chip configured semiconductor die and on the opposing side of the semiconductor die to an interposer substrate to which the semiconductor die is mechanically secured and electrically connected, the structure having a CTE similar to that of the substrate.
U.S. Pat. No. 6,291,899 to Wensel et al. addresses bowing in a COB BGA semiconductor device assembly by applying a so-called stabilizing plate to a side of the substrate opposite that to which the semiconductor die is back side-attached and wire bonded. The stabilizing plate is formed of a rigid material different from that used to encapsulate the semiconductor die and is applied before the encapsulant is applied over the semiconductor die. Placement of the stabilizing plate on the side of the substrate carrying the discrete conductive elements of the BGA also requires fairly precise alignment of the stabilizing plate during placement.
Other U.S. Patents have addressed the issue of stresses in semiconductor packages but only with regard to bowing in lead frame assemblies. For example, U.S. Pat. No. 6,384,487 to Smith and U.S. Pat. No. 6,258,624 to Corisis attempt to equalize the volume of encapsulant material on both sides of a lead frame to minimize bowing. U.S. Pat. No. 6,316,829 to Boon et al. attempts to solve the same problem, but by molding grooves and ridges in an encapsulated lead frame.
While the prior art has attempted to address bowing and other stress-related problems in semiconductor device assemblies, a need exists for a semiconductor device assembly of a design whereby the stresses in the assembly can be controlled effectively while not requiring added process steps or the use of substantial additional materials, expensive materials or complex structural configurations, each of which increase fabrication cost. Further, it would be desirable to provide a semiconductor device assembly design which easily accommodates the use of a BGA for connection to higher-level packaging.